EIPGEN=Val_0x0, DCRCC=Val_0x0, SPEN=Val_0x0, USP=Val_0x0
MAC Extended Configuration Register
| GPSL | Giant Packet Size Limit If the received packet size is greater than the value programmed in this field in units of bytes, the MAC declares the received packet as Giant packet. The value programmed in this field must be greater than or equal to 1,518 bytes. Any other programmed value is considered as 1,518 bytes. For VLAN tagged packets, the MAC adds 4 bytes to the programmed value. When the Enable Double VLAN Processing option is selected, the MAC adds 8 bytes to the programmed value for double VLAN tagged packets. The value in this field is applicable when the GPSLCE bit is set in ETH_MAC_CONFIGURATION register. |
| DCRCC | Disable CRC Checking for Received Packets When this bit is set, the MAC receiver does not check the CRC field in the received packets. When this bit is reset, the MAC receiver always checks the CRC field in the received packets. 0 (Val_0x0): CRC checking is enabled 1 (Val_0x1): CRC checking is disabled |
| SPEN | Slow Protocol Detection Enable When this bit is set, MAC processes the Slow Protocol packets (Ether Type 0x8809) and provides the Rx status. The MAC discards the Slow Protocol packets with invalid sub-types. When this bit is reset, the MAC forwards all error-free Slow Protocol packets to the application. The MAC considers such packets as normal Type packets. 0 (Val_0x0): Slow protocol detection is disabled 1 (Val_0x1): Slow protocol detection is enabled |
| USP | Unicast Slow Protocol Packet Detect When this bit is set, the MAC detects the Slow Protocol packets with unicast address of the station specified in the ETH_MAC_ADDRESS0_HIGH and ETH_MAC_ADDRESS0_LOW registers. The MAC also detects the Slow Protocol packets with the Slow Protocols multicast address (01-80-C2-00-00-02). When this bit is reset, the MAC detects only Slow Protocol packets with the Slow Protocol multicast address specified in the IEEE 802.3-2015 Specification, Section 0 (Val_0x0): Unicast slow protocol packet detection is disabled 1 (Val_0x1): Unicast slow protocol packet detection is enabled |
| EIPGEN | Extended Inter-Packet Gap Enable When this bit is set, the MAC interprets EIPG field and the ETH_MAC_CONFIGURATION[IPG] field together as minimum IPG greater than 96-bit times in steps of 8 bit times. When this bit is reset, the MAC ignores EIPG field and interprets the ETH_MAC_CONFIGURATION[IPG] field as minimum IPG less than or equal to 96-bit times in steps of 8 bit times. Note: The extended Inter-Packet Gap feature must be enabled when operating in Full-Duplex mode only. There may be undesirable effects on back-pressure function and frame transmission if it is enabled in Half-Duplex mode. 0 (Val_0x0): Extended inter-packet gap is disabled 1 (Val_0x1): Extended inter-packet gap is enabled |
| EIPG | Extended Inter-Packet Gap The value in this field is applicable when the EIPGEN bit is set. This field (as Most Significant bits), along with the ETH_MAC_CONFIGURATION[IPG] field, gives the minimum IPG greater than 96-bit times in steps of 8 bit times:{EIPG, IPG} 0x0: 104-bit times 0x1: 112-bit times 0x2: 120-bit times 0xFF: 2144-bit times |